E949 Range Stack TDC

• Fermilab logbook.
  This is an independent source where we try to summarize different RS TDC studies.
• Cabling, Readout, Spare channels
• Turining on power for RS TDC electronics
• MPI logic for RS TDC (Rack L16 Crate 4) PS , xfig source Make sure that internal delay dial on generator that produce MPI DYC signal is set to 1 sec. Otherwise a corrupted signal will be produced which would hang the trigger
• Procedure for RS TDC calibration