SSP code Feb 2002: all_v4.cfg PA: 0x101 File: /fastbus/ssp/trig/ssp_tr2_30e.ssp Option: 0x00000001 Banks: LRID EVCL TRIG TRI2 Comment: PA: 0x102 File: /fastbus/ssp/fera/ssp_dsp_4n_epm.ssp Option: 0x00000000 Banks: SPRA Comment: Fera readout PA: 0x107 File: /fastbus/ssp/tdc/tdc1_v15_epm.ssp Option: 0x00002100 DC <^X00000200> ; option to turn off reading trailing edge data DC <^X00002000> ; REAL mode with CAT DC <^X00000100> ; option to select different ATI values MaxVar: 5000 ModMax: 500 Banks: UTRT Comment: TDC1879 - UTC anodes and cathodes, 21 TDCs. slots 5-25 PA: 0x108 File: /fastbus/ssp/tdc/tdc2_v11_epm.ssp Option: 0x00000000 MaxVar: 5000 ModMax: 500 Banks: BVRT TTRT Comment: TDC1879: BV, 4 TDCs slots 12-15 ; TT,5 TDCs slots 19-23 PA: 0x109 File: /fastbus/ssp/tdc/tdc3_v7_epm.ssp Option: 0x00202020 DC <^X00200000> ; TDC 1876s are wanted DC <^X00000020> ; CAT is NOT wanted DC <^X00002000> ; REAL mode MaxVar: 6000 ModMax: 1000 MarkerName: TDC1876_setup_params MarkerFile: /calib/tdc3/tdc3_all_448_setup.dat Banks: SCT2 BXT2 M1T2 E2T2 Comment: TDC1876: SC:14 tdcs, slots 9-22 BX 4TDCs, slots 23-25,3 M1:beam+CV+IV/VC+misc, slot 5,6 E2 2 TDCs, slots 7-8 PA: 0x103 File: /fastbus/ssp/adc/adc1_v9_epm.ssp Option: 0x1A002020 DC <^X10000000> to enable pedestal suppression DC <^X02000000> ; ADC 1881s are wanted DC <^X08000000> ; load pedestals into ADC 1881 DC <^X00000020> ; CAT is NOT wanted DC <^X00002000> ; REAL mode MaxVar: 2000 ModMax: 75 MarkerName: Pedestal_data_tables MarkerFile: /calib/adc/ped/adc1_ped.dat Banks: UARA RMFA Comment: ADC1881: UA 18 ADCs, slots 8-25 RM 1 ADC slot 7 PA: 0x104 File: /fastbus/ssp/adc/adc2_v9_epm.ssp Option: 0x1A002020 MaxVar: 2000 ModMax: 75 MarkerName: UCRA_pedestal_data MarkerFile: /calib/adc/ped/adc2_ped.dat Banks: UCRA TTFA Comment: ADC1881: UC 15 ADCs, slots 4-18 TT 7 ADCs, slots 19-25 PA: 0x10A File: /fastbus/ssp/comp/comp_ccda_v4_epm.ssp Option: 0x09200000 DC <^X01000000> ; option bit to load pedestal data DC <^X08000000> ; option bit to perform ped checking, DC <^X00200000> ; OPTION BIT - check trig pattern MaxVar: 60000 ModMax: 4500 MarkerName: Pedestal_data_tables MarkerFile: /calib/ccd/ped/load_ccd_pe1.dat Banks: C1CR or C1CP(on TDMON triggers) Comment: PA: 0x10B File: /fastbus/ssp/comp/comp_ccdb_v4_epm.ssp Option: 0x09200000 MaxVar: 60000 ModMax: 4500 MarkerName: Pedestal_data_tables MarkerFile: /calib/ccd/ped/load_ccd_pe2.dat Banks: C2CR or C2CP(on TDMON triggers) Comment: PA: 0x10C File: /fastbus/ssp/comp/comp_ccdc_v4_epm.ssp Option: 0x09200000 MaxVar: 60000 ModMax: 4500 MarkerName: Pedestal_data_tables MarkerFile: /calib/ccd/ped/load_ccd_pe3.dat Banks: C3CR or C3CP(on TDMON triggers) Comment: PA: 0x10D File: /fastbus/ssp/comp/comp_ccdd_v4_epm.ssp Option: 0x09200000 MaxVar: 40000 ModMax: 4500 MarkerName: Pedestal_data_tables MarkerFile: /calib/ccd/ped/load_ccd_pe4.dat Banks : C4CR or C4CP(on TDMON triggers) Comment: PA: 0x201 File: /fastbus/dummy Option: 0x00000000 Banks: see PPC02 who assembles the banks Comment: PA: 0x301 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x29 DC <^X00000001> ; option bit to produce TE** bank DC <^X00000008> ; Crate is a secondary Trigger crate. DC <^X00000020> ; suppress TD bank if trig bit is set MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td1 Banks: LRIF STB3 TD01 TE01 Comment: PA: 0x312 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td2 Banks: TD02 TE02 Comment: PA: 0x314 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td4 Banks: TD04 TE04 Comment: PA: 0x315 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td5 Banks: TD05 TE05 Comment: PA: 0x401 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x29 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td0 Banks: LRIG STB4 TD00 TE00 Comment: PA: 0x413 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td3 Banks: TD03 TE03 Comment: PA: 0x416 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td6 Banks: TD06 TE06 Comment: PA: 0x417 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x21 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td7 Banks: TD07 TE07 Comment: PA: 0x418 File: /fastbus/ssp/td/ssp_tdcb_14e.ssp Option: 0x30 MarkerName: CB_DATA MarkerFile: /fastbus/ssp/td/marker_mult_01_3.td8 Banks: TD08 Comment: PPC01: Banks: At the end of each spill, makes the endspill banks LRID SCAL MONI MONJ MONK MCSC Comment: PPC02: Banks: At the end of each spill, makes the endspill banks LRIE BUF2 and for each event, gets data from 2 VME memories and makes banks STB2 CAR1 CAR2 Comment: PPC03: Banks: At the end of each spill, makes the endspill banks LRIF BUF3 Comment: PPC04: Banks: At the end of each spill, makes the endspill banks LRIG BUF4 Comment: BNLKU9 dr_eb: Banks: For each event, processes bank SPRA adding banks RDPA BVPA E2PA BMPA EHPA ICPA 08PA For endspill events, add banks BUFS EVTI Comment: BNLKU9 dp0: Banks that normally go to tape but it is possibly to "drop" banks according to the options on the command line starting the dp0 Logical record type event LRID EVCL TRIG TRI2 SPRA UARA RMFA UCRA TTFA UTRT BVRT TTRT SCT2 BXT2 M1T2 E2T2 C1CR C2CR C3CR C4CR LRIE STB2 CAR1 CAR2 LRIF STB3 TD01 TE01 TD02 TE02 TD04 TE04 TD05 TE05 LRIG STB4 TD00 TE00 TD03 TE03 TD06 TE06 TD07 TE07 TD08 RDPA BVPA E2PA BMPA EHPA ICPA 08PA Logical record type end_spill LRID SCAL MONI MONJ MONK BUF1 LRIE BUF2 LRIF BUF3 LRIG BUF4 BUFS EVTI