Master Crate

History
-------
  xx-xxx-00 (GR) Created
  02-May-01 (GR) Updated for RSTDC

Slot      Board
----      -----
 0        BBFC
 2        Ancillary logic (not used)
 3        Ancillary logic
 4        Ancillary logic
 5        I/O board
 6        SSP
 8        SSP
10        SSP
14        SFI e787ppc01 CS0
17        SFI e787ppc04 CS3
20        Struck FBD
22        FO2B
23        TD collector
24        TD System Master


I/O board slot 5
----------------

  Output:
    ch 0   CSC enable CS0
       1   CSC enable CS1
       2   CSC enable CS2
       3   CSC enable CS3
      15   CSC external reset

SFI slot 14
-----------
  ECL input 1   SFI Start from IO board in trigger crate


SFI slot 17
-----------
  ECL input 1   SFI start from IO board in TD crate A01


FO2B slot 22
------------

  Input 0    WLRH Long from System Master
        1    WLRH Long from System Master
        2    "L1.n clear to F0"
               comes from somewhere in trigger crate
        3    Clear from CSC
        4    "SSP Start to FO" comes from SQ
        5    BOS

  Output 0
    ch 0-7     to TD's
       8       n/c
       9       to LA
      10       n/c
      11       n/c

  Output 1
    ch 0       n/c
       1       to NIM in Rack L9
       2       n/c
       3       n/c
       4       n/c
       5-11    to TD's

  Output 2
    ch 0       n/c
       1       n/c
       2       to ECL-HIM converter in rack L16
       3       "L1.n clear to TDSM"
       4       n/c
       5       L1.n clear to LA
       6       n/c
       7       cable is hanging in front of UTC anode ADC crate
       8-11    n/c

  Output 3
    ch 0       n/c
       1       to TDSM
       2       n/c
       3       to LA
       4       n/c
       5       n/c
       6       to trigger
       7       n/c
       8       "SSP Clear" goes to NIM-ECL converter in rack L16
       9-11    n/c

  Output 4
    ch 0       n/c
       1       n/c
       2       to LA
       3-4     n/c
       5       "SSP Start to FERA circuit"
       6-9     n/c
       10      to CSC

  Output 5
    ch 0-1     n/c
       2       to IO board ("reset" input) in TD crate 0
       3       to IO board in slot 21 trigger crate
       4-6     n/c
       7       to IO board in TD crate 1


  i Dead time to FO (comes from SQ?)
  o DEad time to LA
  o Dead time to CSC

  i TDSM Clear to FO
  o "TDSM clear from FO to trig"
  o  ditto

        One of these goes nowhere. The other goes to SQ input J2,
        FPIN9 (counting from 1)



System Master v4.0 slot 24
--------------------------

Lemo +       from clock generator (FERA crate slot 23) 125 MHz
Lemo -         "    "       "       "     "    "    "


J1: ch 0     SHEX bit 0 from SCF rack L9
       1     SHEX bit 1
       2     SHEX bit 2
       3     STLAY bit 0  from rack L9
       4               1
       5               2
       6               3
       7-16  n/c

J2: ch 0     n/c
       1     "L0 to TDSM"
       2     "L1.n clear to TDSM"
       3     from FO2B; clear from CSC
       4-16  n/c

J3: ch 0-7   to TDDAC boards (8 bits of SC info?)
              (daisy chain)

J4: ch 0     WLRH Long goes to FO2B input
       1      "    "    "    "   "    "
       2     WLRH to Collector board
       3     n/c
       4     from TDDAC board in TD crate 9 ("R/W crate 9 to TDSM")
       5     ditto
       6     WLRH short gate to LA
       7-15  n/c
       16    TDSM clear to FO2B input

   Also see the diagram on the side of the Master Rack