FERA Master crate

History
-------
  xx-xxx-00 (GR) Created
  02-May-01 (GR) Updated for RSTDC


slot      board
----      -----
 2        STR370 DSP
 5        BFI no longer used
 8        SSP
11        FERA bus fanout
              ("input" cable comes from output of Master FERA driver,
              top crate rack L16)
16        CSC
18        Ancillary logic for CS4
20        SFI e787ppc03 CS4
23        Clock generator
24        Clock fanout
25        Clock fanout


STR370
------

WS1 "FERA write strobe"
      comes from NIM fan-in which OR's the write strobes from each FERA
      driver
I0  "I0 clear DSP0"
I1  "RQ0 DSP0"
      generated when all FERA data has been written into the DSP FIFO

Flat cable in connector DSP0 goes to unknown board in slot 11


CSC
---

Note: black on right unless otherwise noted

J1:  Trig Clear IN 0       comes from IO board in trigger crate
                   1       comes from RSTDC system
                   2       comes from IO board in TD crate 0
                   3                  IO board in TD crate 1
                   4-7     n/c

     CSC enable 0          from IO board in master crate
                1            "      "         "     "
                2            "      "         "     "
                3            "      "         "     "
                4-7        n/c

J2:  Upload request 0      from IO board in trigger crate
                    1           IO board in TD crate 0
                    2           IO board in TD crate 1

        all other J2 pins not connected

External reset:            from IO board in master crate

Manual reset button

SSP start in               from FO2B in master crate

EOS in                     from NIM-ECL converter top crate, rack L9
                            (white on right)

Deadtime                   not sure where it comes from
                           Seems to come from "Clear L1.n" out of SQ
                            (white on right)

J4:  Upload out 0          to IO board in trigger crate
                1             IO board in TD crate 0
                2             IO board in TD crate 1
                3          goes to circuit which vetoes RSTDC stop
                            (rack L6)  (white on right)
      all other pins on J4 not connected

4 NIM SSP start output --> SSP front panel

J5:  First 4 pins n/c
     SSP Start 4?          to "valid in" input of IO board in TD crate 0
               5              "valid in" input of IO board in TD crate 1
               6              "valid in" input of IO board trigger
                                      crate slot 23
               7              "valid in" input of IO board trigger
                                      crate slot 21

     remaining pins n/c


Trig clear out --> to input 3 of FO2B in master crate

EOS out --> to BD board


Clock Generator slot 23
-----------------------

+/-   9th TD crate

+/-   to clock fanout (slot 24)  gets fanned out by 8

+/-   label says "to master oscillator 250 MHz"

+/-   to system master

+/-   to clock fanout (slot 25)  gets fanned out by 8

+/-   to 9th TD crate  (cable seems a bit loose going into connector)

In each TD crate there are 2 fanouts.  Each fanout supplies 4 TD
boards with 2 clock pulses each.