Transient Digitizers

Unambiguous pion identification is essential to assure adequate rejection of muons from even after kinematic constraints are applied. The information required to certify each pion in the range stack is available in the history of pulse shapes from the PMTs which view the scintillator layers in the region of the pion stop. The pion will decay into a monoenergetic (4 MeV) muon and a neutrino, with the muon in turn decaying into a positron (up to 53 MeV) and two neutrinos. In contrast, a stopping muon will lack the 4-MeV signal and decay directly into a positron and two neutrinos.

In order to observe the decay sequence with high acceptance in the scintillator with a typical signal width of 30--40 ns and with the pion lifetime being 26 ns, a sampling rate of s is needed to be able to detect early decays (<10 ns). Since the muon lifetime is 2.2 s, a memory depth of s is needed to insure high efficiency for detection of the muon decay. The required dynamic range of >7 bits is determined by the energy loss in each scintillator of the stopping pion (1 -- 30 MeV), the decay muon (4 MeV), and the decay positron (3 -- 10 MeV). Other necessary features are zero suppression to keep the number of data words reasonable, fast data readout in a standard format to keep deadtime low at high rates, and access to front-end high-speed computing for data compaction and on-line trigger decisions.

A system of -sample s, 8-bit transient digitizers (TD) [16] was constructed to meet these specifications. The range-stack signals are multiplexed by summing corresponding layers from four adjacent sectors into one TD channel. At this level, random background rates and signal degradation are not significant problems. Since the detailed information this system offers is also valuable for other detector systems (e.g. photon veto and target) in improving acceptance and accidental rejection, the system is expandable and other channels have been added as they have become available.

The system is housed in Fastbus, supporting up to eight 4-channel modules per crate. Each crate contains a control board (TDMaster) used to read out the data from the 32 channels over a special high-bandwidth bus on the auxiliary backplane, and transfer the data on the main Fastbus backplane to a SLAC Scanner Processor (SSP) [17] crate master. In addition, each crate houses two 500-MHz clock fanout boards. Cooling of each 1.6-kW crate is by forced air through water-cooled heat exchangers.

Fig. 13

 
Figure 13: Block diagram of one channel of the 500-MHz digitizer.  

shows a block diagram of the basic digitizing channel. It consists of four parts: the flash ADC, the custom data handling chip, fast memories and data acquisition/readout protocol electronics. Flash ADCs offer the important features of ability to suppress zeros prior to writing and of fast access to the data, as well as the possibility of a large memory depth. The effective dynamic range can be increased, for example, by using bilinear conversion or logarithmic signal processing on the input.

Each channel in the system uses a Tektronix ADC hybrid TKAD508 consisting of a 500-MHz sample-and-hold circuit and two interleaved 250-MHz ADCs shown schematically in Fig. 13. The device requires two differential analog inputs to the Sample-and-Hold, a 500-MHz clock signal, and two reference voltages to the ADCs. The sample-and-hold drives the two ADCs and supplies the necessary clocking and buffering. The output of the hybrid is a pair of interleaved bytes of data at a rate of 250 MHz. One byte is output on the rising edge of the clock, while the other is output on the falling edge of the clock. The device is capable of 7.2 effective bits performance at 100 MHz, and 6.8 effective bits at 250 MHz.

The negative polarity PMT signal is fed to one analog input, and the other input is set at a DC level generated by one of the 32 12-bit Digital-to-Analog converters (DAC) contained on the TDMaster board. This allows fine software control on the effect of the digital threshold to provide zero suppression by compensating small DC voltage shifts in the input signals. The settable DAC levels also provide an efficient means of on-line testing and calibration. This method of using the device provides an input dynamic range of up to 1 V. In addition, a fiducial time marker derived from the trigger is induced on the DC level.

A custom IC (BNL787TD) called the macrocell was designed to handle the high data rate (2 bytes every 4 ns), to provide zero suppression of flash ADC data prior to writing into memory, and to carry out the various housekeeping and digital readout duties required in such a device. The macrocell is a time demultiplexer capable of handling input data rates of up to 400 MHz (but normally runs at 250 MHz), implemented in Signetics ACE2200 current-mode-logic technology and has roughly 2150 gate equivalents. It takes as input 2 bytes of data and a synchronizing clock signal and outputs 4 bytes of data at half the input frequency. In addition the IC generates two identical 8-bit addresses for the external memory and an 8-bit timing marker generated by an internal timer. The output of the timer labels the data words with their relative timing, necessary because of the zero-suppression feature of the system.

The external memory is 4-ns Hitachi HM10422-7 256 x 4 ECL. The data word width is 48 bits: 32 bits of data, 8 bits of time and 8 bits of flags to identify the 4 multiplexed PMT signals in each TD channel. To reduce the load on the address lines from the macrocell, the twelve memories per channel are organized into two banks of 6 memories (hence the two identical address-line sets generated by the macrocell).

The memory for each channel forms a circular buffer, with zero-suppressed data overwriting old data until a trigger is received. Typically, data from -3 s to +6 s with respect to the K decay is saved. Zero suppression is achieved by incrementing the memory address only for data bytes exceeding 7 counts as well as for one adjacent byte before and after. The memory depth is extended beyond that afforded by the 8-bit timer (2 s) by forcing a write to memory whenever the timer counter overflows. Other conditions which synchronize the data to a trigger from the detector, and special diagnostic states also cause the memory address to be incremented to store data. The extension of the timer data to greater than 2 s and the rearrangement of the data is done subsequent to readout in software at the crate level.

Crate-level intelligence is used to form high-level triggers on-line based on the TD data. The crate controller (SSP) is a special purpose integer-arithmetic computer with roughly 5 -- 10 Mips of computing power. In addition, a special front-end processor was developed to handle the raw data from each channel prior to being read out by the SSP. This module, called the Transient Digitizer Smart Controller (TDSC), uses an AMD 29K pipeline RISC processor with separate data, address and I/O busses and a compatible floating point co-processor, and is capable of about twice the effective computing power of the SSP.

The transient digitizer system is used for both on-line trigger and off-line separation. Fig. 14

 
Figure 14: TD data from four adjacent range-stack layers, showing the pulses for a pion entering from the bottom, stopping in layer 14, decaying to a muon, and finally the muon decaying to a positron.  

shows the power of correlated time/pulse-height measurements in a typical event. The penetrated through several range-stack layers, stopped in layer 14, decayed into a muon, and the muon subsequently decayed into a positron which penetrated several more layers.

Fig. 15

 
Figure 15: TD data from a stopping pion showing the second pulse from the decay to a muon. Analytical fits to (a) two pulses and (b) one pulse, from which / particle identification is done.  

shows the data from the stopping layer. One can clearly see the primary pulse with the secondary muon decay. In the simplest algorithm to separate pions from muons on-line, a test on the ratio of pulse-area to pulse-peak-value is done and a minimum value is required which tends to reject single pulses (muons) and accept double pulses (pions). This technique typically accepts 72% of pions and rejects 86% of muons.

In off-line analysis, the pulse-shape data are tested for goodness-of-fit to a single-pulse (muon) or a two-pulse (pion) hypothesis as illustrated in Fig. 15. From a successful two-pulse fit one can extract the energy and time of the secondary muon. The curve in Fig. 16a

 
Figure 16: (a) Energy spectrum for the 4-MeV from decay from TD data. (b) End-to-end time difference for the decay and (c) decay from TD data.  

shows a 15% energy resolution on the 4-MeV muon, due to a combination of the basic resolution of the device and the fitting-scheme resolution. Reduction of random backgrounds is achieved by comparing the timing of the secondary and tertiary pulses relative to the primary pulse on both ends of the range-stack counter. The end-to-end timing resolution from data for the secondary pulse (muon) is shown in Fig. 16b, and for the tertiary pulse (positron) in Fig. 16c. Fig. 17

 
Figure 17: Pion decay-time spectrum from TD data showing the lifetime fit.  

shows a distribution of the secondary pulse time relative to the primary pulse compared to the pion lifetime of 26.1 ns. The dropoff at times <8 ns costs about 25% in decay detection efficiency. The final rejection achieved using both the secondary and tertiary pulse detection is about .