The logic of the trigger system initiates signal digitizing in the data acquisition system. After Level 1, the higher levels of trigger decision involve close links with the data acquisition in order to minimize the large overhead invested in reading out and logging the data. The process up to the point of reading the front-end data into SSP memory in each Fastbus crate was described in the previous section. Once the decision is made (after Level 2) to collect and format the data in the SSPs, the data path continues in the data acquisition system in four stages as indicated in Fig. 23.
Figure 23: Block diagram of the data acquisition system.
Each stage is performed by a different microprocessor and runs asynchronously from the others. As long as no stage saturates its allotted time, only the first stage contributes to the dead time.
Stage 1 is the event-by-event readout. During each beam spill from the AGS, acquisition of the data is done independently in each secondary Fastbus crate for all events that pass the trigger. The data are collected by an SSP and stored in its data memory (512 Kbytes). The only communication between Fastbus crates is done via the Fastbus cable segment to synchronize the event number, to acknowledge completion of the readout in each crate and to report possible errors.
The limitations at this stage come from the conversion time of the front-end modules, the size of the data memory of each SSP, the speed of the SSPs, and the amount of data formatting required. For the moderate data rates possible in the present configuration of the experiment, the 8-ms time for this step has not been critical because the trigger decision was fast enough that most events were rejected before it was necessary to format them.
The second stage occurs during the period (typically 1.6 s)
between beam spills.
Data are collected from each crate over the Fastbus cable segment and events
are assembled in memory by a Master SSP. Events are then dispatched to the
memory of an available node in the VME ACP [23] system via the Branch Bus,
using a Fastbus Branch Coupler.
The data transfer rate on the Fastbus cable segment is about 18 Mbyte s
and on the Branch Bus about 15 Mbyte s
. The typical
event length at this stage is 20 kbytes.
At the third stage an array of up to 24 ACP microprocessor nodes, located in two VME crates controlled by a host VAX [24], is used to reject events (functioning as the Level 3 trigger) and to compress the data. Each node uses a Motorola 68020 processor and 2 Mbytes of memory. Processing in the nodes has been limited primarily to compression of TD data resulting in a factor of two reduction in the event size, and to some analysis of special test and calibration triggers. For example, TD channels which contained only the fiducial time marker were cut. The system has the potential to perform analysis and apply conservative cuts equivalent to a first pass off-line analysis.
In the final stage, the data are collected from the nodes by the ACP host
Q-bus [24] computer, stored in memory and copied to tape by independent
processes. Extra records containing calibration and control information
are added.
At this stage the bandwidth limitations come mostly from the Q-bus
which must handle all transfers from VME to
memory, from memory to tape, all disk activity and
all DECNET/ETHERNET activity. An effective throughput of
180 Kbyte s
to tape is presently achieved.
On-line monitoring of detector performance and data quality was done by transferring samples of events from the host VAX over DECNET [24] to other VAX nodes running analysis and display software similar to the off-line packages. For example, this on-line package produces occupation plots of detector subsystems, and monitors parameters such as rates, gains, event lengths, and persistant missing channels, with the purpose of quickly identifying failures in the detector, trigger, and data acquisition systems.