An event trigger is refined in four stages of increasing sophistication and decision time. The first two stages, Level 0 and Level 1, are executed in a custom-built system of ECL logic boards [22] designed around the configuration of the range stack, but including the essential input from the beam, target and photon-veto systems. The K-stop logic is formed externally in fast NIM logic from the beam scintillators and Cerenkov counters and a discriminated analog sum of the target-fiber signals. Level 0 is entirely composed of fast combinational logic, and introduces about 40 ns of deadtime per event. Level 1 is implemented in memory lookup units (MLU), and takes several microseconds to make a decision. Trigger decisions beyond Level 1 involve arithmetic processing of ADC and TD data. In Level 2 the ADC data from the range-stack track are selected and summed in CAMAC in a few tens of microseconds and arithmetic processing in Fastbus of the TD data requires about 150 microseconds. Level 3 applies loose cuts and compacts the data in about 500 microseconds. The latter will be described further with the Data Acquisition system in the next section.
Low-level triggers are classified into groups depending on which of two
timing strobes are used to issue gate signals to the various detector systems.
The beam strobe, related to a stopping kaon, is formed in NIM logic and
determined by the kaon Cerenkov time.
The detector strobe, related to a charged particle entering the fiducial
volume of the range stack, is formed in the trigger system using the
discriminated PMT signals from the T and A layers from all
24 sectors. For each sector, the mean time from the two ends of A
defines the time for a 
coincidence, which is then ORed from all
sectors to form the detector strobe.
Cable lengths were trimmed to keep sector-to-sector jitter to <1 ns.
The physics triggers, 
kaon decays, as well as range-stack calibration
and beam-background studies, use both strobes, but are initiated by
the detector strobe. A schematic
diagram of the Level 0 system is shown in Fig. 22.
Figure 22: Block diagram of the Level 0 trigger system.
A 
stopping in the target decays into a 
that produces a 
when it
enters the range stack. The range (stopping layer) of the 
is deduced by
the Range Cards (RC1B), each of which takes the discriminator signals
from one complete range-stack sector, and
determines layers belonging to a positive-charged track.
Pulse heights from the range stack segmented into hextants, barrel veto
and endcaps are summed and discriminated to produce veto signals, which
are latched and placed on the 48-line Trigger Bus
by the Trigger Transmitter (TT1A).
The stopping layer information from the Range Cards is also latched onto the
Trigger Bus, along with external conditions from the beam and target systems,
to establish a minimum decay time with respect to a 
stop,
and topology information from a fast MLU which recognizes valid
patterns of 
hits.
Up to 16 Level 0 triggers
can be implemented using ECL logic chips on wire-wrap Trigger Boards (TB1B)
that make decisions based on the state of the Trigger Bus.
For example, the Level 0 trigger for 
requires, in addition to
a 
coincidence, an incident 
(identified by the Cerenkov) to have stopped in the fiducial volume
of the target and decayed after the minimum-time condition (determined
from the B4, target, I-, and V- counters),
a charged-particle track in the range stack that penetrated into
layer B, but not to layer 19 or beyond, and no energy above threshold
in the photon-veto system.
The information on the Trigger Bus is updated with every 
until
any of the Trigger Boards find a match and issues a 50-ns-long interim inhibit
(DT) signal to the Trigger Transmitter which freezes the Trigger Bus until the
Level 0 signal has had time to propagate through its Prescaler (PS1A)
channel, the AND/OR board (AO1A) , and the Sequencer (SQ1A). The prescaling
factor is adjustable from 1 to 
.
If the prescaler output is true, the Sequencer will issue beam
and detector strobes via Delay-Width-Fanout boards (DF1A)
to the appropriate ADCs and
TDCs, send a signal to initiate Level 1, and set a flip-flop
which further extends the DT signal.
The information transmitted by the AND/OR board verifies that the Level 0 and Level 1 triggers are of the same kind, and that the relative timing of the Level 0 and 1 signals are correct. Both the Trigger Bus and the AND/OR Board are read by receiver boards (TR1A), which feed the data to I/O boards in Fastbus to be accessed by the SSP crate master as seven 32-bit trigger words which summarize the Level 0 and Level 1 trigger results, as well as bus and MLU status for every defined trigger type. These data eventually form part of an event written to tape.
Cosmic ray triggers (for barrel-veto calibration) require only the detector
strobe, while beam triggers require only the beam strobe.
These triggers are much simpler, since they essentially bypass
the Range Card and Trigger Bus structures, and do not involve Level 1.
A special board is used to latch the prescaled beam trigger and output
the proper strobes and levels to the Sequencer and I/O boards.
The cosmic triggers, based on 
and I-counter hits recognized
in a fast MLU board, are also prescaled and fed through a special board
to the Sequencer and I/O boards.
There is also provision for external triggers, carrying their own
strobe timing, 
the endcap-veto 
calibration trigger.
External triggers are input via a ``Bells & Whistles'' (BW1A) board
which generates the required timing
strobes and handles all communication with the Sequencer and I/O boards.
The other function performed by the BW1A board is to verify
correct ADC gate timing, and SSP starts, and it is able to generate a
clear signal to the Sequencer, for trigger-system testing
without the need for computer intervention.
In the case of 
, the Level 1
decision is based on a refined range measurement taking into account the
polar angle of the 
, and the range in the target.
An MLU address is created out of the z position of a hit in an RSPC by
converting the end-to-end timing difference to an analog level and digitizing
it to a 4-bit word with a flash ADC. This takes about 
s and
gives a position resolution of 
10 mm.
The range of the 
or 
in the target, can be
deduced from the number of struck target elements
which is also flash digitized to a 4-bit word.
These, together
with another 4 bits of stopping layer
information derived from the Level 0 Trigger Bus,
make up the 12-bit address to a second MLU whose
contents determine the Level 1 trigger decision.
If a Level 1 false is returned, a reset
is issued to restart the TDCs and clear the ADCs
without interrupting the SSPs.
If the Level 1 decision is true, the Sequencer initiates Level 2 by sending a start signal to the Fastbus trigger SSP which instructs the secondary SSPs to read out the LRS CAMAC 4300B FERA ADCs and LRS Fastbus 1879 TDCs, and to the TDSCs in the TD system. Level 2A is performed during the readout of the ADCs. A charged-track energy sum is formed by digitally adding the ADC outputs of the target and range-stack counters as they are transferred from the CAMAC modules to a Fastbus buffer memory via a front panel ECL readout port. LRS ECLine modules (LRS 2372 MLU and LRS 2378 ALU) are used to screen out information from non-track-associated ADCs and to perform the sum to which a maximum energy cut is applied.
In parallel with the Level 2A process in CAMAC, the raw TD data are
processed in Level 2B by the TDSCs
resident in the TD Fastbus crates.
The TD pulse-shape information from the range-stack
stopping counter is analyzed for evidence of a second pulse indicative
of decay of the stopped pion. Only events with a separated
second pulse or with a pulse-height to pulse-area ratio consistent with
a single pulse augmented by 
decay are retained.
Prior to the implementation of TDSCs, the pulse-analysis algorithm was
executed in the SSPs after the TD data were read out.
For each event that passes both Level 2A and Level 2B, data are
collected in memory by the SSPs in each Fastbus crate for
further processing by the data acquisition system. The trigger Sequencer
receives a clear signal from the Fastbus Master SSP and then issues
the reset to the ADCs and TDCs. After waiting 7 
s for the
resetting to finish, the DT signal to the Trigger Transmitter is cleared
and the trigger is restarted.
Table I
Table I: Typical Trigger and Data Acquistion for 
summarizes typical trigger and data acquisition performance
for 
triggers only at a rate of 
per
1.6-s AGS beam spill. In practice, additional physics and monitor
triggers are suitably prescaled and added up to a maximum deadtime
fraction of 30 -- 35%.